This invention relates to arrangements for controlling the range of addresses of memory available to a processor.
Problem:
One of the basic limitations of a processor system is the range of memory which can be attached to the central processing unit of the processor. In many modern processors, memory is basically dedicated to the instructions for controlling the processor (program), and the data on which the processor operates. In many such processors, efficiency is increased by having separate communities of program stores and data stores accessed by separate buses. In such cases, the program stores and the data stores have non-overlapping ranges of addresses of their memories. For certain operations, it is desirable to treat the contents of some of the program memory as data, and/or to treat the contents of some of the data memory as instructions. For example, if there is a failure in the program store community, the analysis of the failure is best carried out under the control of instructions supplied by the data store community. In the case of a failure of the data store community, it is desirable that the program store community store data concerning the maintenance status of the data store community. Therefore, in order to enhance the reliability of the system, it is best to have a single range of storage addresses which covers all of the addresses of both the program store community and the data store community. This is, in fact, what is done, for example, in the electronic switching systems, such as the 4 ESS(trademark)Switch, manufactured by Lucent Technologies Inc.
A problem arises because the range of addresses for instructions and for data may not be adequate for particular applications.
Solution:
The above problem is solved and an advance is made over the teachings of the prior art in accordance with Applicants"" invention, wherein the boundary between instructions and data can be controlled by internal registers of a processor, and can, therefore, be moved; thus, providing more data or more instruction storage as needed for particular applications. In accordance with Applicants"" preferred embodiment, a limited high-speed storage system providing, for example, 1 mega-word of storage can be configured to provide, for example, 25%, 50%, or 75% instruction storage, with the rest being data storage. In this preferred embodiment, additional lower speed storage is provided to meet the demands of the many applications that need much more than 1 mega-word of storage. Advantageously, using this arrangement, applications which require heavy use of more instruction storage can be handled efficiently, as can applications which require heavy use of a larger amount of data storage, by dynamically reconfiguring the memory allocation for each application.
In accordance with this preferred embodiment, this arrangement is combined with another arrangement, wherein a processor has at least two modes of operation; one mode being the mode for using restricted address capabilities of the present processor, a second mode for using a much greater range of addresses, but restricted to the use of separate program and data addresses for respective separate program and data store communities. Applicants believe that the bulk of the software which requires the use of data from a program store community, and/or instructions from a data store community, are in the carry-over software necessary for maintaining the processor system, and that software and data for controlling the operation of additional services, and storing the data for these additional services, can be restricted to separate program and data store communities in which no instructions are stored in the data stores and no data is stored in the program stores. Advantageously, the availability of the two modes of operation, allows the carry-over software to be retained and executed in the first mode, and allows software for controlling a much larger address range of program and data stores to be executed in the second mode.
In accordance with one preferred embodiment of Applicants"" invention, a first mode exists wherein all memory addressing is over the initial address range. This mode is particularly useful for executing carry-over software. When in this mode, an address in the instruction range generated by a instruction address generator, will cause an instruction to be fetched from the instruction range. If the address generated by the instruction address generator is in the data range, then that instruction is fetched from the data portion of the base memory range. In accordance with this preferred embodiment, there are separate buses associated with the instruction range and the data range. Therefore, if an instruction is fetched from an address in the data range, this instruction must be fetched using the data access bus.
Similarly, if a word of data is to be accessed from the data range, this word would be accessed using the data access bus. If data is to be accessed in the instruction range, then that data is accessed using the instruction access bus.
In accordance with the second mode of accessing memory, which constitutes Applicants"" invention, if a second mode control is set, then when an instruction is fetched, but the unextended portion of the address is in the base data range, then that instruction is fetched using an extended address whose extension is specified by an instruction segment selector.
Similarly, in the alternate mode of memory accessing, if a data access is specified, the unextended portion of whose address is in the base instruction range, then the data is accessed from the address specified, but extended with the contents of a data segment selector.
However, in the second mode, if an instruction carries an address that is in the instruction range, then that instruction is fetched from the instruction range of the base memory; similarly, in the second mode, if a data access is executed whose address is in the data range of the base memory, then that data is accessed from the data portion of the base memory. This allows for easy access to the base range of memory.
Advantageously, using this type of arrangement, the range of memory that can be accessed by a processor is limited not by the addressing range of the central processing unit, but by the size of the address bus used for accessing memory. In Applicants"" particular embodiment, the base range is 8 mega words of memory, but the address buses together allow up to 1,024 mega words of memory to be addressed.